The Marvell Fast Ethernet physical layer (PHY) transceivers offer the industry’s lowest power dissipation, smallest form factor, highest performance, and the most advanced feature set. The octal members of the Fast Ethernet PHY family, the 88E3082 and 88E3083 devices, significantly lead the industry with the lowest power consumption (under 150 mWatts per port), enabling network systems manufacturers to decrease system cost by reducing both power supply and fan requirements.
The Fast Ethernet PHYs transceivers feature the Marvell Virtual Cable Tester® (VCT) technology, allowing end-users, IT managers and networking equipment manufacturers to analyze quickly and remotely the quality and attributes of the cable, avoiding unnecessary equipment returns and on-site service calls.
RTL8201 Ethernet PHY chip
The Microchip LAN9250/LAN935x provides design solutions ta rgeted to support next generat ion Ethernet switches and a 10/100 Industrial Ethernet MAC/PHY controller. The Ethernet switch products are divided into host bus and MII cate-gories with the host bus version supporting a full featured Et hernet MAC residing behind t he switch fabric. DownloadGuide ethernet switch phy chips pdf. Get file Kahn reported that J. New members can be placed in a pending status until approved. Guide ethernet switch phy chips pdf Guide ethernet switch phy chips pdf Direct Link #1 That works extremely well and is very intuitive. 2012098D-EEE9-4769-8DD3-B038050854D4 Version 3.
A PHY, an abbreviation for 'physical layer', is an electronic circuit, usually implemented as a chip, required to implement physical layer functions of the OSI model.
A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable. A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality.[1]
Ethernet physical transceiver[edit]
Micrel KS8721CL - 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver
The Ethernet PHY is a component that operates at the physical layer of the OSI network model. It implements the Ethernet physical layer portion of the 1000BASE-T, 100BASE-TX, and 10BASE-T standards.
A PHY chip (PHYceiver) is commonly found on Ethernet devices. Its purpose is to provide analog signal physical access to the link. It is usually with a Media Independent Interface (MII) interfaced to a MAC chip in a microcontroller or other system that takes care of the higher layer functions.
More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling.[2] The PHY usually does not handle MAC addressing, as that is the link layer's job. Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.
Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers and offerings from Intel[3] and ICS.[4]
Other applications[edit]
Wireless LAN or Wi-Fi: The PHY portion consists of the RF, mixed-signal and analog portions, that are often called transceivers, and the digital baseband portion that use digital signal processor (DSP) and communication algorithm processing, including channel codes. It is common that these PHY portions are integrated with the media access control (MAC) layer in System-on-a-chip (SOC) implementations. Other similar wireless applications are 3G/4G/LTE, WiMAX, UWB, etc.
Universal Serial Bus (USB): A PHY chip is integrated into most USB controllers in hosts or embedded systems and provides the bridge between the digital and modulated parts of the interface.
IrDA: The Infrared Data Associations (IrDA) specification includes an IrPHY specification for the physical layer of the data transport.
Serial ATA (SATA): Serial ATA controllers use a PHY.
References[edit]
^Mauricio Arregoces; Maurizio Portolani. 'Data Center Fundamentals'. Books.google.com. Retrieved 2015-11-18.
^'microcontroller - what is the difference between PHY and MAC chip - Electrical Engineering Stack Exchange'. Electronics.stackexchange.com. 2013-07-11. Retrieved 2015-11-18.